PCI-Recorder  Audio-Schnittstellenkarte für den PCI-Bus, Teil 2 Martin Kirst, Uwe Kirst

Bild 8. VHDL-Code für das Modul 'pipcon'.

library ieee;
use ieee.std_logic_1164.all;

entity pipcon is
  port (CLK, PCI_REQ, PCI_GNT, LOC_REQ, LOC_GNT, WRrd : 
                                           in std_logic;
        TRDY_SM, WRGATE, INC_ADDR, SRD_T, SROEn, load, ack : 
                                           out std_logic);
end pipcon;

architecture pipcon_arch of pipcon is

  type state is (Idle, FstWrt, WrBurst, RdPip1, RdPip2, RdBurst,
                                           Read, Write);
  signal current_state, next_state : state;
  signal y : std_logic_vector (1 to 7);

begin

  state_logic : process (current_state, PCI_REQ, PCI_GNT, LOC_REQ, 
                                            LOC_GNT, WRrd)
  begin
    case current_state is

      when Idle =>
        if (LOC_REQ = '1' and LOC_GNT = '1') then
          next_state <<= Read;
          y <= "0011010";
        elsif (PCI_REQ = '0' or PCI_GNT = '0') then
          next_state <= Idle;
          y <= "0001000";
        elsif (WRrd = '1') then
          next_state <= FstWrt;
          y <= "1011000";
        else
          next_state <= RdPip1;
          y <= "0001100";
        end if;

      when FstWrt =>
        next_state <= WrBurst;
        y <= "0010000";

      when WrBurst =>
        if (PCI_REQ = '0') then
          next_state <= Idle;
          y <= "0011000";
        else
          next_state <= WrBurst;
          y <= "0110100";
        end if;

      when RdPip1 =>
        next_state <= RdPip2;
        y <= "0001100";

      when RdPip2 =>
        next_state <= RdBurst;
        y <= "1001100";

      when RdBurst =>
        if (PCI_REQ = '0') then
          next_state <= Idle;
          y <= "0001000";
        else
          next_state <= RdBurst;
          y <= "0001100";
        end if;

      when Read =>
        next_state <= Write;
        y <= "0010001";

      when Write =>
        next_state <= Idle;
        y <= "0011000";

    end case;
  end process;


  state_register : process begin
    wait until (CLK'event and CLK = '1');
    current_state <= next_state;
    (SROEn, SRD_T, INC_ADDR, load, ack) <= std_logic_vector'(y(3 to 
                                                    7));
  end process;

  (TRDY_SM, WRGATE) <= std_logic_vector'(y(1 to 2));

end pipcon_arch;