Epson created several RAM Disk units for the PX-8 and PX-4. For the PX-8 the original is a 60 kByte and a 120 kByte RAM Disk. These are so called 'Intelligent' as there is a Z80 processor with firmware which handles request from the PX-8. This is the RAM Disk variant mentioned in the User Manual and Technical Manual. The 'Intelligent' RAM Disk uses I/O ports 80h and 81h.
The Operating System Reference Manual also has info on the 'Non-Intelligent' RAM Disk. These devices didn't exist as stand-alone device but were combined with other devices like the 'Japanese-language processing unit', ROM capsules, direct modem or the 'Synchronous communication unit'. The 'Non-Intelligent' RAM Disk is I/O mapped, and uses ports to specify the address and read/write data. One extra port is used for the Command/Status registers. One extra feature makes this device not trival to recreate; the lower address byte is self- incrementing,after each read or write, the value is incremented. So each successive data read/write will use the next memory location. This allows for fast reading and writing (processor OTIR and INIR instructions). The 'Non-Intelligent' RAM Disk uses I/O ports 90h to 94h.
For the PX-4 there appears to be only a RAM Disk of the 'Non-Intelligent' type. It is combined with the 64k-bit to 1-Mbit ROM capsule. The port usage is the same as for the PX-8. The addressing space, accessed with the three address registers, is divided between RAM (00000h-1FFFFh) and ROM (20000h-3FFFFh). The ROM capsule is not checked or managed by the O.S. but needs user software.
It is notable all Epson made RAM Disks use dynamic RAM, probablty the most economic option in the 1980s. It is nice that there are better options now.
These are the interesting parts of the RAM Disk hardware:
The Addrdec GAL is mainly an address decoder with a timing signal generator on the spare pins.
The Rincrementer GAL has two modes; loading a new value in the registers and increment the eight bits. The difference is made by the level of the /LOAD signal at the rising edge of the clock. The loading of a new value is triggered by the /WLOAD (not-Write LOw ADdress byte). /WLOAD is extended by an SR-flipflop and the end is the /M1 of the next instruction. The other signal is the /DATCS siglal used to read and write a byte from the RAM. The address should be stable at the rising edge of the /RD or /WR signal. Here the best option seems to be a delay the GAL CLK signal. An SR-flipflop generates the /DlyDATCS from /DATCS. Some spare pins and gates of the AddressDecoder GAL combine the normal /WLOAD clock with the extended /DATCS clock. They both end with the falling edge of /M1, so will not interfere with the CPU data transfers (occurring at 'M2' and up).
The image below shows the various signal timings made with PulseView/sigrok. It also shows the very cool Z80 signal interpreter.
The alogorithm to properly increment eight bits is surprisingly simple:
The pulse extenders use a basic SR-flipflop.
The RAM Disk is now functionally complete and minimally tested with the PX-8 and PX-4. The main issue is the orientation of the connectors, so the board is upside-down, with both computers. A version 1.4 is already designed to fix this problem and other optimisations.
Another issue is that there battery is not on the board. This might not be an issue when some form of non-volatile RAM is used or a properly connected battery.
There is no case for it. It remains to be seen if it is possible to create a nice looking box, usable for both computers.
The write protect is not properly implemented. According to the PX-8 Operating System Reference Manual, page 16-8, the increment function should be disabled when Write Protect (switch and/or register) is active. Protection against writing to RAM is implemented in the ADDRDEC7 GAL with the WP signal.
The schematic could be simplified a bit. When this fix is tested and new boards are produced (and tested too), board production data will be published here. I will not sell build boards.
Quite late in the process, I discovered the function of the OPN signal. For bytes to be read or written to RAM, the refresh for the DRAM (in all Epson RAM Disk variants!) must be halted. It also enables the LSB auto- increment for RAM. As RAM refresh is not used for static RAM, the OPN signal is not useful. Disabling the auto-increment might be sort-of memory protection, but making it switchable for just the lower 128 kByte would require more circuitry.
Even if the code for a larger RAM-Disk never materialises, an extra RAM chip at the 20000h-3FFFFh range can be used as the 1 Mbit ROM with an easy way to program it :-).
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Updated: 2025-10-19