Based on P800M Instruction Set (Extended Specification) Pub No. 5122 991 27366, January 1982 and P856M/P857M System Handbook, Pub No. 5122 991 26932, April 1976, ch. 7. This list excludes the P857M specific Floating-Point instructions. r1, r2, r3 - k - constant (8-bit) lk - long constant (16-bit) m - memory location cnd - condition n - bit positions addr - memory location Condition codes 'cnd' (bits 10,9,8): G - greater than xx1 L - less than x1x Z - zero 1xx NZ - Not Zero 0xx EQ - Equal 1xx NE - Not Equal 0xx 7 111 Operand type T1 Register/Register - Format 1 (short) The operand is the value in the register specified by R2 of the instruction format. T2 Long Constant - Format 1 (long) R2 == 0 The operand is the value in the least significant word, all sixteen bits, of the double length instruction format. T3 Address in Register - Format 1 (short) R2 <> 0, Address in R2 The operand is held in memory. The memory address of the operand is the value in the register specified by R2 of the instruction format. T4 Address in Next Word - Format 1 (long) R2 == 0, Address in next word The operand is held in memory. The memory address of the operand is the value in the least significant word of the double length instruction. T5 Indexed Address in Next Word - Format 1 (long) R2 <> 0, Indexed The operand is held in memory. The memory address of the operand is found by adding the value in the register specified by R2 of the instruction format to the value in the least significant word of the double length instruction. T6 Indirect Address in Next Word - Format 1 (long) R2 == 0, Indirect The operand is held in memory. The memory address of the operand is also held in memory. This indirect address is the value in the least significant word of the double length instruction. T7 Indexed Indirect Address in Next Word - Format 1 (long) R2 <> 0, Indexed indirect The operand is held in memory. The memory address of the operand is also held in memory. This indirect address is found by adding the value in the register specified by R2 of the instruction format to the value in the least significant word of the double length instruction. T8 Short Constant - Format 0 The operand is the value in the least significant eight bits of the instruction format. AB Absolute conditional branch AB [cnd] k T8 ABI Absolute branch indirect ABI cnd[*] m [,r2] T4 - T7 ABL Absolute conditional branch long ABL [cnd] lk T2 ABR Absolute branch to register ABR cnd[*] r2 T1, T3 AD Addition AD[*] r1, m [,r2] T4 - T7 ADK Add constant ADK r3, k T8 ADKL Add constant long ADK r1, lk T2 ADR Addition register/register ADR[*] r1, r2 T1, T3 ADRS Addition register/register ADRS r1, r2 T3 ADS Addition ADS[*] r1, m [,r2] T4 - T7 ANKL Logical and with constant long ANKL r1, lk T2 ANK Logical and with constant ANK r3, k T8 AN Logical AND AN[*] r1, m [,r2] T4 - T7 ANR Logical AND register/register ANR[*] r1, r2 T1, T3 ANRS Logical AND register/register ANRS r1, r2 T3 ANS Logical AND ANS[*] r1, m [,r2] T4 - T7 C1 Ones complement C1[*] r1, m [,r2] T4 - T7 C1R Ones complement register/register C1R[*] r1, r2 T1, T3 C1RS Ones complement register/register C1RS r2 T3 C1S Ones complement C1S[*] m [,r2] T4 - T7 C2R Twos complement register/register C2R r2 T3 C2 Twos complement C2[*] m [,r2] T4 - T7 CC Compare characters CC[*] r1, m [,r2] T4 - T7 CCK Compare character with constant CCK r1, lk T2 CCR Compare character/register CCR r1, r2 T3 CF Call function CF r1, lk T2 CFI Call function indirect CFI[*] r1, m [,r2] T4 - T7 CFR Call function register CFR[*] r1, r2 T1, T3 CIO Control Input/Output CIO T8 CM Clear memory CM[*] m [,r2] T4 - T7 CMR Clear memory/register CMR r2 T3 CW Compare words CW[*] r1, m [,r2] T4 - T7 CWK Compare word with constant CWK r1, lk T2 CWR Compare words register/register CWR[*] r1, r2 T1, T3 DA Double add DA[*] m [,r2] T4 - T7 DAK Double add with constant DAK lk1, lk2 T2 DAR Double add register/register DAR[*] r2 T1, T3 DLA Double left and arithmetic shift DLA n T8 DLC Double left and circular shift DLC n T8 DLL Double left and logical shift DLL n T8 DLN Double left and normalize shift DLN r2 T8 DRA Double right and arithmetic shift DRA n T8 DRC Double right and circular shift DRC n T8 DRL Double right and logical shift DRL n T8 DRN Double right and normalize shift DRN r2 T8 DS Double subtract DS[*] m [,r2] T4 - T7 DSK Double subtract with constant DSK lk1, lk2 T2 DSR Double subtract register/register DSR[*] r2 T1, T3 DV Divide DV[*] m [,r2] T4 - T7 DVK Divide by constant DVK lk T2 DVR Divide register/register DVR[*] r2 T1, T3 EBN Enable EBN T8 ECR Exchange characters register/register ECR r1, r2 T1 EL Extended Load (MMU) EL T4 - T7 ELR Extended Load Register (MMU) ELR T3 ES Extended Store (MMU) ES T4 - T7 ESR Extended Store Register (MMU) ESR T3 EX Execute EX[*] m [,r2] T4 - T7 EXK Execute constant EXK lk T2 EXR Execute register EXR[*] r2 T1, T3 HLT Halt Halt T8 INH Inhibit Interrupt INH T8 IM Increment memory IM[*] m [,r2] T4 - T7 IMR Increment memory/register IMR r2 T3 INR Input to Register INR T8 LCK Load character with constant LCK r1, lk T2 LC Load character LC[*] r1, m [,r2] T4 - T7 LCR Load character/register LCR r1, r2 T3 LDA Load address LDA r1, D, r2 T1 LDKL Load constant long LDKL r1, lk T2 LDK Load constant LDK r3, k T8 LD Load Register LD[*] r1, m [,r2] T4 - T7 LDR Load register/register LDR[*] r1, r2 T1, T3 LKM Link To Monitor LKM T8 MLK Multiple load constant MLK n T2 ML Multiple load ML[*] n, m [,r2] T4 - T7 MLR Multiple load/register MLR n, r2 T3 MS Multiple store MS[*] n, m [,r2] T4 - T7 MSR Multiple store register MSR n, r2 T3 MUK Multiply with constant MUK lk T2 MU Multiply MU[*] m [,r2] T4 - T7 MUR Multiply register/register MUR[*] r2 T1, T3 MVB Move Table Backward (P857 standard) MVB T8 MVF Move Table Forward (P857 standard) MVF T8 MVSU Move Table From System to User (MMU) MVSU T8 MVUS Move Table From User to System (MMU) MVUS T8 NGR Negate register NGR r1, r2 T1 ORKL Logical OR with constant long ORKL r1, lk T2 ORK Logical OR with constant ORK r3, k T8 OR Logical OR OR r1, m [,r2] T4 - T7 ORR Logical OR register/register ORR[*] r1, r2 T1, T3 ORRS Logical OR register/register ORRS r1, r2 T3 ORS Logical OR ORS[*] r1, m [,r2] T4 - T7 OTR Output from Register OTR T8 RB Relative backwards conditional branch RB [cnd] m T8 RER Read external register RER r3, addr T8 RF Relative forward conditional branch RF [cnd] m T8 RIT Reset Internal Interrupt RIT T8 RTN Return from function (A0-14) RTN r2 T3 RTN Return from function (A15) RTN A15 T3 SCR Store character/register SCR r1, r2 T3 SC Store character SC[*] r1, m [,r2] T4 - T7 SLA Single left and arithmetic shift SLA r3, n T8 SLC Single left and circular shift SLC r3, n T8 SLL Single left and logical shift SSL r3, n T8 SLN Single left and normalize shift SLN r3, r2 T8 SMD Set Mode SMD T8 SRA Single right and arithmetic shift SRA r3, n T8 SRC Single right and circular shift SRC r3, n T8 SRL Single right and logical shift SRL r3, n T8 SRN Single right and normalize shift SRN r3, r2 T8 SST Send Status SST T8 STR Store register/register STR r1,r2 T3 ST Store register ST[*] r1, m [,r2] T4 - T7 SUKL Subtract constant long SUKL r1, lk T2 SUK Subtract constant SUK r3, k T8 SURS Subtract register/register SURS r1, r2 T3 SUR Subtract register/register SUR[*] r1, r2 T1, T3 SUS Subtract word SUS[*] r1, m [,r2] T4 - T7 SU Subtract word SU[*] r1, m [,r2] T4 - T7 TBR Test Bit/Register TBR r2 T3 TB Test Bit TB[*] m [,r2] T4 - T7 TL Segment Table Load (MMU) TL T4 - T7 TLR Segment Table Load Register (MMU) TLR T3 TS Segment Table Store (MMU) TS T4 - T7 TSR Segment Table Store Register (MMU) TSR T3 TM Test mask TM r1, r2 T1 TNM Test not mask TNM r1, r2 T1 TRBR Test and Reset Bit/Register TRBR r2 T3 TRB Test and Reset Bit TRB[*] m [,r2] T4 - T7 TSBR Test and Set Bit/Register TSBR r2 T3 TSB Test and Set Bit TSB[*] m [,r2] T4 - T7 TST Test Status TST T8 WER Write external register WER r3, addr T8 XR Exclusive OR XR[*] r1, m [,r2] T4 - T7 XRK Exclusive OR with constant XRK r3, k T8 XRKL Exclusive OR with constant long XRKL r1, lk T2 XRR Exclusive OR register/register XRR[*] r1, r2 T1, T3 XRS Exclusive OR XRS[*] r1, m [,r2] T1, T3 XRRS Exclusive OR register/register XRRS r1, r2 T3 Latest update: 2025-11-08